1. Field of the Invention
This invention relates generally to serial-parallel-serial charge-coupled devices and more particularly to a redundant fault-correctable device and a method of making same.
2. Description of the Prior Art
Charge-coupled device (CCD) structures for use in data processing system storage and communication signal processing are well known in the art. Referring to the patents and publications listed below under the heading "Reference Cited By Applicant," Boyle and Smith [Refs. 1, 10, 11] originally disclosed the basic charge-coupled concept. Weimer [Ref. 2] disclosed the serial-parallel-serial arrangement. Tompsett [Ref. 3] reviewed further early work, including the serial-parallel-serial configuration. Collins et al. [Ref. 4] disclosed a serial-parallel-serial structure with double-level metallization. Carnes, Kosonocky and Sauer [Refs. 5, 12] disclosed further advances including two-phase operation, buried channel structures, and applications to analog signal processing and image sensors.
In a serial-parallel-serial configuration, a data bit stream is injected into a serial CCD shift register from where it is transferred in parallel to a parallel storage section. The data can then be shifted in parallel through the parallel section, and then transferred in parallel to an output serial register, from where it is shifted out as a serial bit stream.
The parallel section comprises a large matrix of storage sites each adapted to serve as a potential well for storing a packet of charge carriers. Because of the large number of storage sites in the many rows and columns of the matrix, there is a substantial probability that at least one site is defective. As presently practiced in the art, the occurrence of even a single defective site requires that the entire chip be rejected and scrapped.
This approach substantially reduces the manufacturing yield and therefore substantially increases the cost of charge-coupled devices. Because the cost per stored bit is a critical factor in the determination of whether charge-coupled devices are competitive with other storage technologies it is vitally important that the yield of charge-coupled device manufacture be improved by every feasible means.
In efforts to improve the yield of charge-coupled devices and other semiconductor memory chips, numerous "fault tolerant" schemes have been proposed. For example, Elmer et al. [Refs. 9, 13, 14] disclose charge-coupled device memories wherein the address circuitry is modified so as to bypass an entire array of registers or an entire block of arrays. These arrangements are disadvantageous in that the required redundancy is large. That is, a single defective storage site results in the non-utilization of an entire array or block and the necessity for an extra redundant array or block to be provided for the substitution. Furthermore, the address modification structure for bypassing defective arrays or blocks is slow in operation if of the serial addressing type or relatively complex if of the parallel addressing type.
In the prior art of random access memories there have been many schemes for fault tolerance with only moderate redundancy. That is, the presence of a single defective cell requires the substitution of only a redundant row or column of cells, instead of an entire array or block. Choate and Bhandarkar [Ref. 15] refer to many prior art patents disclosing such arrangements. However, these are "address translation" schemes and are pertinent to memories which operate in an addressed random access mode as distinguished from the serial mode of charge-coupled devices. Furthermore, these schemes present all of the disadvantages of cost and complexity involved in the additional logic required for the address translation from the addresses of bad bits to the addresses of good bits.